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quad-channel isolators with integrated dc-to-dc converter ADUM5401W/adum5402w/adum5403w rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features iso power integrated, isolated dc-to-dc converter qualified for automotive applications regulated 5 v output up to 500 mw output power quad dc-to-25 mbps (nrz) signal isolation channels 16-lead soic package with 7.6 mm creepage high temperature operation: 105c high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul1577 csa component acceptance notice #5a vde certificate of conformity (pending) din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak applications hybrid electric battery management general description the ADUM5401W/adum5402w/adum5403w 1 devices are quad-channel digital isolators with iso power?, an integrated, isolated dc-to-dc converter. based on the analog devices, inc., i coupler? technology, the dc-to-dc converter provides up to 500 mw of regulated, isolated power at 5.0 v. this eliminates the need for a separate, isolated dc-to-dc converter in low power, isolated designs. the i coupler chip-scale transformer technology is used to isolate the logic signals and for the magnetic components of the dc-to-dc converter. the result is a small form factor, total isolation solution. the ADUM5401W/adum5402w/adum5403w isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the ordering guide for more information). iso power uses high frequency switching elements to transfer power through its transformer. special care must be taken during printed circuit board (pcb) layout to meet emissions standards. refer to the an-0971 application note for board layout recommendations at www.analog.com . functional block diagrams 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc rect 4 channel i coupler core v dd1 reg gnd 1 v ia /v oa v ib /v ob v ic /v oc v od rc out gnd 1 v iso gnd iso v oa /v ia v ob /v ib v oc /v ic v id v sel gnd iso ADUM5401W/adum5402w/ adum5403w 08758-001 figure 1. ADUM5401W/adum5402w/adum5403w block diagram 3 4 5 6 14 13 12 11 ADUM5401W 08758-002 v ia v ib v oa v ob v ic v oc v od v id figure 2. ADUM5401W 3 4 5 6 14 13 12 11 adum5402w 08758-003 v ia v ib v oa v ob v oc v ic v od v id figure 3. adum5402w 3 4 5 6 14 13 12 11 adum5403w 08758-004 v ia v ob v oa v ib v oc v ic v od v id figure 4. adum5403w 1 protected by u.s. patents 5,952,849; 6,873,065; 6, 903,578; and 7,075,329. other patents are pending.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics5 v primary input supply/5 v secondary isolated supply .......................................................... 3 ? package characteristics ............................................................... 5 ? regulatory approvals ................................................................... 5 ? insulation and safety-related specifications ............................ 5 ? din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 6 ? recommended operating conditions ...................................... 6 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configurations and function descriptions ........................... 8 ? truth table .................................................................................. 11 ? typical performance characteristics ........................................... 12 ? terminology .................................................................................... 14 ? applications information .............................................................. 15 ? theory of operation .................................................................. 15 ? pcb layout ................................................................................. 15 ? thermal analysis ....................................................................... 15 ? propagation delay-related parameters ................................... 16 ? emi considerations ................................................................... 16 ? dc correctness and magnetic field immunity ........................... 16 ? power consumption .................................................................. 17 ? power considerations ................................................................ 17 ? insulation lifetime ..................................................................... 18 ? v iso startup issues ...................................................................... 19 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 1/10revision 0: initial version
ADUM5401W/adum5402w/adum5403w rev. 0 | page 3 of 20 specifications electrical characteristics5 v primary in put supply/5 v secondary isolated supply all typical specifications are at t a = 25c, v dd1 = v iso = 5 v. minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 v v dd1 , v iso 5.5 v, and ?40c t a +105c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 1. dc-to-dc converter static specifications parameter symbol min typ max unit test conditions dc-to-dc converter supply setpoint v iso 4.7 5.0 5.4 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 50 ma, v dd1 = 4.5 v to 5.5 v load regulation v iso (load) 1 5 % i iso = 10 ma to 90 ma output ripple v iso (rip) 75 mv p-p 20 mhz bandwidth, c bypass = 0.1 f||10 f, i iso = 90 ma output noise v iso (noise) 200 mv p-p c bypass = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pw modulation frequency f pwm 625 khz output supply current i iso (max) 100 ma v iso > 4.5 v efficiency at i iso (max) 34 % i iso = 100 ma i dd1 , no v iso load i dd1 (q) 20 35 ma i dd1 , full v iso load i dd1 (max) 290 ma table 2. dc-to-dc converte r dynamic specifications parameter symbol 25 mbps unit test conditions min typ max supply current input ADUM5401W i dd1 68 ma no v iso load adum5402w i dd1 71 ma no v iso load adum5403w i dd1 75 ma no v iso load available to load ADUM5401W i iso (load) 87 ma calculated adum5402w i iso (load) 85 ma calculated adum5403w i iso (load) 83 ma calculated table 3. switching specifications parameter symbol 25 mbps unit test conditions min typ max switching specifications data rate 25 mbps limited by maximum pwd propagation delay t phl , t plh 45 60 ns 50% input to 50% output pulse width distortion pwd 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 40 ns limited by maximum pwd propagation delay skew t psk 15 ns between any two units channel matching codirectional 1 t pskcd 6 ns opposing directional 2 t pskod 15 ns 1 7 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inpu ts on the same side of the isolation barrier. 2 opposing directional cha nnel matching is the absolute value of the difference in propagation delays between any two channels w ith inputs on opposing sides of the isolation barrier.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 4 of 20 table 4. input and output characteristics parameter symbol min typ max unit test conditions dc specifications logic high input threshold 1 v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold 1 v il 0.3 v iso or 0.3 v dd1 v logic high output voltages 2 v oh v dd1 ? 0.3 or v iso ? 0.3 5.0 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages 2 v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout v dd1 , v iso supply positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v input currents per channel i il , i ih ?20 +0.01 +20 a 0 v v ix v ddx or v iso ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 3 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 v sel is a nonstandard input that has a lo gic threshold of approximately 0.9 v. 2 rc out is a nonstandard output intended to interface with other iso power parts. it is not recommended for standard digital loads. 3 |cm| is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd1 or 0.8 v iso for a high input or v o < 0.8 v dd1 or 0.8 v iso for a low input. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 5 of 20 package characteristics table 5. thermal and isolation characteristics parameter symbol min typ max unit test conditions resistance (input to output) 1 r i-o 10 12 capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to ambient thermal resistance ja 45 c/w thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 3 1 the device is considered a 2-terminal device; pin 1 to pin 8 are shorted together, and pin 9 to pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. 3 see the sectio n for thermal model definitions. thermal analysis regulatory approvals table 6. ul 1 csa vde (pending) 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 single protection, 2500 v rms isolation voltage basic insulation per csa 60950-1-03 and iec 60950-1, 400 v rms (566 v peak) maximum working voltage reinforced insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each ADUM5401W/a dum5402w/adum5403w is proof tested by applying an in sulation test voltage 3000 v rms for 1 second (current leakage detection limit = 10 a). 2 in accordance with din v vde v 0884-10, each adum540xw is proof te sted by applying an insulation test vo ltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884-10 approval. insulation and safety-related specifications table 7. critical safety-related di mensions and material properties parameter symbol value unit test conditions/comments rated dielectric insulation voltage 2500 v rms 1-minute duration minimum external air gap (clearance) l(i01) >8.0 mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.7 mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303, part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
ADUM5401W/adum5402w/adum5403w rev. 0 | page 6 of 20 din v vde v 0884-10 (vde v 0884-10) insulation characteristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety d ata is ensured by the protective circuits. the asterisk (*) marking on packages denotes din v vde v 0884-10 approval. table 8. vde characteristics description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 sec v tr 4000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 5 ) case temperature t s 150 c side 1 i dd1 current i s1 555 ma insulation resistance at t s v io = 500 v r s >10 9 08758-005 0 100 200 300 400 500 600 0 50 100 150 200 ambient temperature (c) safe operating v dd1 current (ma) figure 5. thermal derating curve, dependence of safety limi ting values on case temperature, per din en 60747-5-2 recommended operat ing conditions table 9. parameter symbol min max unit operating temperature 1 t a ?40 +105 c supply voltages 2 v dd1 4.5 5.5 v 1 operation at 105c requires redu ction of the maximum load current, as specified in . table 10 2 each voltage is relative to its respective ground.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 7 of 20 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 10. parameter rating storage temperature (t st ) ?55c to +150c ambient operating temperature range (t a ) ?40c to +105c supply voltages (v dd , v iso ) 1 ?0.5 v to +7.0 v v iso supply current 2 t a = ?40c to +85c 100 ma t a = ?40c to +105c 60 ma input voltage (v ia , v ib , v ic , v id ) 1, 3 ?0.5 v to v ddi + 0.5 v output voltage (rc out , v oa , v ob , v oc , v od ) 1, 3 ?0.5 v to v ddo + 0.5 v average output current per data output pin 4 ?10 ma to +10 ma maximum cumulative ac hipot 5 min @ 2500 v rms maximum cumulative dc hipot 5 min @ 3500 v dc common-mode transients 5 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective grounds. 2 the v iso provides current for dc and dynamic loads on the v iso i/o channels. this current must be included when determining the total v iso supply current. for ambient temperatures between 85c and 105c, maximum allowed current is reduced. 3 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pcb layout section. 4 see figure 5 for the maximum rated current values for various temperatures. 5 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 11. maximum continuous working voltage supporting 50-year minimum lifetime 1 parameter max unit applicable certification ac voltage bipolar waveform 424 v peak all certifications, 50-year operation basic insulation 560 v peak working voltage per iec 60950-1 unipolar waveform basic insulation 560 v peak working voltage per iec 60950-1 dc voltage basic insulation 560 v peak working voltage per iec 60950-1 1 refers to the continuous voltage magnitude imposed across the isol ation barrier. see the insulation lifetime sect ion for more information. esd caution
ADUM5401W/adum5402w/adum5403w rev. 0 | page 8 of 20 pin configurations and function descriptions v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 rc out 7 v sel 10 gnd 1 8 ADUM5401W top view (not to scale) 08758-006 gnd iso 9 figure 6. ADUM5401W pin configuration table 12. ADUM5401W pin function descriptions pin o. mnemonic description 1 v dd1 primary supply voltage, 4.5 v to 5.5 v. pin 1 and pin 7 must be connected to the same external voltage source. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in of a slave iso power device to allow the ADUM5401W to control the regulation of the slave device. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v sel this pin must be connected to v iso for proper operation of the part. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output, 5.0 v for external loads.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 9 of 20 v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v 5 oc v 12 ic v od 6 v id 11 rc out 7 v sel 10 gnd 1 8 adum5402w top view (not to scale) 08758-007 gnd iso 9 figure 7. adum5402w pin configuration table 13. adum5402w pin function descriptions pin o. mnemonic description 1 v dd1 primary supply voltage, 4.5 v to 5.5 v. pin 1 and pin 7 must be connected to the same external voltage source. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in of a slave iso power device to allow the ADUM5401W to control the regulation of the slave device. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v sel this pin must be connected to v iso for proper operation of the part. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output, 5.0 v for external loads.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 10 of 20 v dd1 1 gnd 1 2 v ia 3 v ob 4 v iso 16 gnd iso 15 v oa 14 v ib 13 v 5 oc v 12 ic v od 6 v id 11 rc out 7 v sel 10 gnd 1 8 adum5403w top view (not to scale) 08758-008 gnd iso 9 figure 8. adum5403w pin configuration table 14. adum5403w pin function descriptions pin o. mnemonic description 1 v dd1 primary supply voltage, 4.5 v to 5.5 v. pin 1 and pin 7 must be connected to the same external voltage source. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ob logic output b. 5 v oc logic output c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in of a slave iso power device to allow the ADUM5401W to control the regulation of the slave device. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v sel this pin must be connected to v iso for proper operation of the part. 11 v id logic input d. 12 v ic logic input c. 13 v ib logic input b. 14 v oa logic output a. 16 v iso secondary supply voltage output, 5.0 v for external loads.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 11 of 20 truth table table 15. truth table (positive logic) v ix input 1 v dd1 state v dd1 input (v) v iso state v iso output (v) v ox output 1 notes high powered 5.0 powered 5.0 high normal operation, data is high low powered 5.0 powered 5.0 low normal operation, data is low 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d).
ADUM5401W/adum5402w/adum5403w rev. 0 | page 12 of 20 typical performance characteristics 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 0.02 0.04 0.06 0.08 0.10 0.12 08758-009 output current (a) efficiency (%) 5v input/5v output figure 9. typical power supply efficiency at 5 v/5 v 08758-010 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.020.040.060.080.100.1 i iso (a) power dissipation (w) 2 v dd1 = 5v, v iso = 5v figure 10. typical total power dissipation vs. i iso with data channels idle 0 0.02 0.04 0.06 0.08 0.10 0.12 0 0.05 0.10 0.15 0.20 0.25 0.35 0.30 input current (a) output current (a) 08758-011 5v input/5v output figure 11. typical isolated output supply current, i iso , as a function of external load, no dynamic current draw at 5 v/5 v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3 .5 4.0 4 .5 5.0 5 .5 6.0 6 .5 input supply voltage (v) input cur r ent (a) power (w) i dd1 power 08758-012 figure 12. typical short-circuit input current and power vs. v dd1 supply voltage 08758-013 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load figure 13. typical v iso transient load response, 5 v output, 10% to 90% load step 08758-014 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load figure 14. typical transient load response, 3 v output, 10% to 90% load step
ADUM5401W/adum5402w/adum5403w rev. 0 | page 13 of 20 08758-015 bw = 20mhz (400ns/div) 5v output ripple (10mv/div) figure 15. typical v iso = 5 v output voltage ripple at 90% load 0 4 8 12 16 20 051 01 5 data rate (mbps) supply current (ma) 20 25 08758-016 5v input/5v output figure 16. typical i chn supply current per forward data channel (15 pf output load) 0 4 8 12 16 20 051 01 5 data rate (mbps) supply current (ma) 20 25 08758-017 5v input/5v output figure 17. typical i chn supply current per reverse data channel (15 pf output load) 051 01 5 data rate (mbps) supply current (ma) 20 25 5v 08758-018 0 2 1 3 4 5 figure 18. typical i iso (d) dynamic supply current per input 0 1.0 0.5 1.5 2.0 2.5 3.0 051 01 5 data rate (mbps) supply current (ma) 20 25 5v 08758-019 figure 19. typical i iso (d) dynamic supply current per output (15 pf output load)
ADUM5401W/adum5402w/adum5403w rev. 0 | page 14 of 20 terminology i dd1 (q) i dd1 (q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operating below 2 mbps, requiring no additional dynamic supply current. i dd1 (q) reflects the minimum current operating condition. i dd1 (d) i dd1 (d) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. resistive loads on the outputs should be treated separately from the dynamic load. i dd1 (max) i dd1 (max) is the input current under full dynamic and v iso load conditions. i iso (load) i iso (load) is the current available to an external v iso load. t phl propagation delay t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. t psk propagation delay skew t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. t pskcd /t pskod channel-to-channel matching channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 15 of 20 applications information theory of operation the dc-to-dc converter section of the ADUM5401W/adum5402w/ adum5403w works on principles that are common to most modern power supplies. it is a secondary side controller architecture with isolated pulse-width modulation (pwm) feedback. v dd1 power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. power transferred to the secondary side is rectified and regulated to 5 v. the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v dd1 ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. the ADUM5401W/adum5402w/adum5403w implement undervoltage lockout (uvlo) with hysteresis on the v dd1 power input. this feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates. a minimum load current of 10 ma is recommended to ensure optimum load regulation. smaller loads can generate excess noise on chip due to short or erratic pwm pulses. excess noise generated this way can cause data corruption, in some circumstances. pcb layout the ADUM5401W/adum5402w/adum5403w digital isolators with 0.5 w iso power integrated dc-to-dc converters require no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 20 ). note that a low esr bypass capacitor is required between pin 1 and pin 2 as well as between pin 15 and pin 16, as close to the chip pads as possible. the power supply section of the ADUM5401W/adum5402w/ adum5403w uses a 180 mhz oscillator frequency to efficiently pass power through its chip-scale transformers. in addition, normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required for several operating frequencies. noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. these are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v iso . to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 and v iso . a 10 nf capacitor should be used when optimum emi emissions performance is desired. the smaller capacitors must have a low esr; for example, use of an npo ceramic capacitor is advised. note that the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 2 mm. installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. a bypass between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless both common ground pins are connected together close to the package. v dd1 gnd 1 v ia v ib /v ob v iso gnd iso v oa v ob /v ib v ic /v oc v oc /v ic v od rc out v id v sel gnd 1 bypass < 2mm gnd iso 08758-020 figure 20. recommended printed circuit board layout in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in table 10 , thereby leading to latch-up and/or permanent damage. the ADUM5401W/adum5402w/adum5403w are power devices that dissipate about 1 w of power when fully loaded and running at maximum speed. because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the pcb through the ground pins. if the devices are used at high ambient temperatures, provide a thermal path from the ground pins to the pcb ground plane. the board layout in figure 20 shows enlarged pads for pin 8 and pin 9. large diameter vias should be implemented from the pad to the ground, and power planes should be used to reduce inductance. multiple vias in the thermal pads can significantly reduce temperatures inside the chip. the dimensions of the expanded pads are left to the discretion of the designer and the available board space. thermal analysis the ADUM5401W/adum5402w/adum5403w parts consist of four internal die attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, the die is treated as a thermal unit, with the highest junction temperature reflected in the ja from table 5 . the value of ja is based on measurements taken with the parts mounted on a jedec standard, 4-layer board with fine width traces and still air. under normal operating conditions, the ADUM5401W/adum5402w/adum5403w devices operate at full load across the full temperature range without derating the output current. however, following the recommendations in the pcb layout section decreases thermal resistance to the pcb, allowing increased thermal margins in high ambient temperatures.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 16 of 20 propagation delay related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see figure 21 ). the propagation delay to a logic low output may differ from the propagation delay to a logic high. input ( v ix ) output (v ox ) t plh t phl 50% 50% 08758-021 figure 21. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADUM5401W/adum5402w/adum5403w component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADUM5401W/ adum5402w/adum5403w components operating under the same conditions. emi considerations the dc-to-dc converter section of the ADUM5401W/ adum5402w/adum5403w components must, of necessity, operate at a very high frequency to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. grounded enclosures are recommended for applications that use these devices. if grounded enclosures are not possible, follow good rf design practices in the layout of the pcb. see www.analog.com for the most current pcb layout recommendations specifically for the ADUM5401W/adum5402w/adum5403w. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be not powered or nonfunctional, in which case, the isolator output is forced to a default high state by the watchdog timer circuit. this situation should only occur during power-up and power-down operations. the limitation on the ADUM5401W/adum5402w/adum5403w magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the pulses at the transformer output have an amplitude of >1.0 v. the decoder has a sensing threshold of about 0.5 v, thus estab- lishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d /dt ) r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the ADUM5401W/ adum5402w/adum5403w, and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 22 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 08758-022 figure 22. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 17 of 20 the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADUM5401W/ adum5402w/adum5403w transformers. figure 23 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 23 , the ADUM5401W/ adum5402w/adum5403w are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example, a 0.5 ka current placed 5 mm away from the ADUM5401W/adum5402w/ adum5403w is required to affect component operation. magnetic field frequency (hz) maximum allowable current (ka) 1k 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 08758-023 figure 23. maximum allowable current for various current-to-ADUM5401W/adum5402w/adum5403w spacings note that, in combinations of strong magnetic field and high frequency, any loops formed by pcb traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. exercise care in the layout of such traces to avoid this possibility. power consumption the v dd1 power supply input provides power to the i coupler data channels, as well as to the power converter. for this reason, the quiescent currents drawn by the power converter and the primary and secondary i/o channels cannot be determined separately. all of these quiescent power demands have been combined into the i dd1 (q) current, as shown in figure 24 . the total i dd1 supply current is equal to the sum of the quiescent operating current; the dynamic current, i dd1 (d) , demanded by the i/o channels; and any external i iso load. converter primary converter secondary primary data input/output 4-channel i ddp(d) e secondary data input/output 4-channel i iso(d) i iso i dd1(q) i dd1(d) 0 8758-024 figure 24. power consumption within the ADUM5401W/adum5402w/adum5403w dynamic i/o current is consumed only when operating a channel at speeds higher than the refresh rate of f r . the dynamic current of each channel is determined by its data rate. figure 16 shows the current for a channel in the forward direction, meaning that the input is on the v dd1 side of the part. figure 17 shows the current for a channel in the reverse direction, meaning that the input is on the v iso side of the part. both figures assume a typical 15 pf load. the following relationship allows the total i dd1 current to be calculated: i dd1 = ( i iso v iso )/( e v dd1 ) + i chn ; n = 1 to 4 (1) where: i dd1 is the total supply input current. i chn is the current drawn by a single channel determined from figure 16 or figure 17 , depending on channel direction. i iso is the current drawn by the secondary side external load. e is the power supply efficiency at 100 ma load from figure 9 at the v iso and v dd1 condition of interest. the maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. i iso (load) = i iso (max) ? i iso (d)n ; n = 1 to 4 (2) where: i iso (load) is the current available to supply an external secondary side load. i iso (max) is the maximum external secondary side load current available at v iso . i iso (d)n is the dynamic load current drawn from v iso by an input or output channel, as shown in figure 18 and figure 19 . the preceding analysis assumes a 15 pf capacitive load on each data output. if the capacitive load is larger than 15 pf, the additional current must be included in the analysis of i dd1 and i iso (load) . power considerations the ADUM5401W/adum5402w/adum5403w power input, data input channels on the primary side, and data channels on the secondary side are all protected from premature operation by uvlo circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations. during application of power to v dd1 , the primary side circuitry is held idle until the uvlo preset voltage is reached. at that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 18 of 20 when the primary side is above the uvlo threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. the outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary power is established. the primary side oscillator also begins to operate, transferring power to the secondary power circuits. the secondary v iso voltage is below its uvlo limit at this point; the regulation control signal from the secondary is not being generated. the primary side power oscillator is allowed to free run in this circumstance, supplying the maximum amount of power to the secondary, until the secondary voltage rises to its regulation setpoint. this creates a large inrush current transient at v dd1 . when the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. the v dd1 current is reduced and is then proportional to the load current. the inrush current is less than the short-circuit current shown in figure 12 . the duration of the inrush depends on the v iso loading conditions and the current available at the v dd1 pin. as the secondary side converter begins to accept power from the primary, the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. secondary side inputs sample their state and transmit it to the primary side. outputs are valid about 1 s after the secondary side becomes active. because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care with the design to allow the converter sufficient time to stabilize before valid data is required. when power is removed from v dd1 , the primary side converter and coupler shut down when the uvlo level is reached. the secondary side stops receiving power and starts to discharge. the outputs on the secondary side hold the last state that they received from the primary side. either the uvlo level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches uvlo. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. analog devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADUM5401W/adum5402w/ adum5403w. accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined, allowing calcu- lation of the time to failure at the working voltage of interest. the values shown in table 11 summarize the peak voltages for 50 years of service life in several operating conditions. in many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. operation at working voltages higher than the service life voltage listed leads to premature insulation failure. the insulation lifetime of the ADUM5401W/adum5402w/ adum5403w depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 25 , figure 26 , and figure 27 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. a 50-year operating lifetime under the bipolar ac condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 11 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross-insulation voltage waveform that does not conform to figure 26 or figure 27 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in table 11 . 0v r a ted pe a k v oltage 08758-025 figure 25. bipolar ac waveform 0v r a ted pe a k v oltage 08758-026 figure 26. dc waveform 0v r a ted pe a k v oltage notes 1. the voltage is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0v. 0 8758-027 figure 27. unipolar ac waveform
ADUM5401W/adum5402w/adum5403w rev. 0 | page 19 of 20 solution v iso startup issues the slew rate of v iso is determined by the resistive and capacitive load present on the output. designs that attempt to reduce ripple by adding capacitance to the v iso output can slow the slew rate enough to see startup errors. choose values for bulk capacitance based on the effective dc load. calculate the dc load as the resistive equivalent to the current drawn from the v iso line. determine the range of allowable capacitance for the v iso output from figure 28 . choose the bulk capacitance for v iso to achieve the applications required ripple, unless the value is in the disallowed combinations area, then the value has to be reduced to avoid restart issues. an issue with reliable startup has been identified in the ADUM5401W/5402w/5403w components. it is related to initialization of the band gap voltage references on the primary (power input) and secondary (power output) sides of the iso power device and are being addressed in future revisions of the silicon. for current versions of the silicon, the user must follow these design guidelines to guarantee proper operation of the device. the band gap voltage references are vulnerable to slow power- up slew rate. the susceptibility to power-up errors is process sensitive so not all devices display these behaviors. these recommendations should be implemented for all designs until the corrections are made to the silicon. the symptoms and corrective actions required for issues with the primary and secondary side startup are different. 100k 10k 1k 100 10 1 11 0 c viso (f) 100 1k r viso ( ? ) disallowed combinations 08758-028 symptom the v iso output voltage restarts to an incorrect voltage between 3.4 v and 4.7 v when power is removed at v dd1 and then reapplied between 250 ms and 3 sec later. the error only occurs on restart, it does not occur at initial power-up. if the part initializes incorrectly, power must be remove for an extended time to allow internal nodes to discharge and reset. the amount of time required can be several minutes at low temperature; therefore, it is critical to avoid allowing the device to initialize improperly. cause figure 28. maximum capacitive load for proper restart the secondary side band gap reference does not initialize to the proper voltage due to a slow slew rate on v iso after the internal nodes are precharged during the previous power cycle. the secondary side band gap sets the output voltage of the regulator.
ADUM5401W/adum5402w/adum5403w rev. 0 | page 20 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 29. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v iso side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range package description package option ADUM5401Wcrwz 3 1 25 60 6 ?40c to +105c 16-lead soic_w rw-16 adum5402wcrwz 2 2 25 60 6 ?40c to +105c 16-lead soic_w rw-16 adum5403wcrwz 1 3 25 60 6 ?40c to +105c 16-lead soic_w rw-16 1 z = rohs compliant part. 2 tape and reel are available. the addition of an rl suffix designates a 13 (1,000 units) tape and reel option. ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08758-0-1/10(0)

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